Chapter 5 The Instruction Set Architecture Level

5.1 Overview of the ISA Level

5.1.1 Properties of the ISA Level

5.1.2 Memory Models

5.1.3 Registers

5.1.4 Instructions

5.1.5 Overview of the Pentium 4 ISA Level

5.1.6 Overview of the UltraSPARC III ISA Level

5.1.7 Overview of the 8051 ISA Level

5.2 Data Types

5.2.1 Numeric Data Types

5.2.2 Nonnumeric Data Types

5.2.3 Data Types on the Pentium 4

5.2.4 Data Types on the UltraSPARC III

5.2.5 Data Types on the 8051

5.3 Instruction Formats

5.3.1 Design criteria for Instructional Formats

5.3.2 Expanding Opcodes

5.3.3 The Pentium 4 Instructional Formats

5.3.4 The UltraSPARC III Instructional Formats

5.3.5 The 8051 Instructional Formats

5.4 Addressing

5.4.1 Addressing Modes

5.4.2 Immediate Addressing

5.4.3 Direct Addressing

5.4.4 Register Addressing

5.4.5 Register Indirect Addressing

5.4.6 Indexed Addressing

5.4.7 Based-Indexed Addressing

5.4.8 Stack Addressing

5.4.9 Addressing Modes for Branch Instructions

5.4.10 Orthogonality of Opcodes and Addressing Modes

5.4.11 The Pentium 4 Addressing Modes

5.4.12 The UltraSPARC III Addressing Modes

5.4.13 The 8051 Addressing Modes

5.4.14 Discussion of Addressing Modes

5.5 Instruction Types

5.5.1 Data Movement Instructions

5.5.2 Dyadic Operations

5.5.3 Monadic Operations

5.5.4 Comparisons and Conditional Branches

5.5.5 Procedure Call Instructions

5.5.6 Loop Control

5.5.7 Input/Output

5.5.8 The Pentium 4 Instructions

5.5.9 The UltraSPARC III Instructions

5.5.10 The 8051 Instructions

5.5.11 Comparison of Instructional Sets

5.6 Flow of Control

5.6.1 Sequential Flow of Control and Branches

5.6.2 Procedures

5.6.3 Coroutines

5.6.4 Traps

5.6.5 Interrupts

 

5.7 A Detailed Example: The Towers of Hanoi

5.7.1 Towers of Hanoi in Pentium 4 Assembly Language

5.7.2 Towers of Hanoi in UltraSPARC III Assembly Language

5.8 The IA-64 Architecture and the Itanium 2

5.8.1 The Problem with the Pentium 4

5.8.2 The IA-64 Model: Explicitly Parallel Instruction Computing

5.8.3 Reducing Memory References

5.8. 4Instruction Scheduling

5.8.5 Reducing Conditional Branches: Prediction

5.8.6 Speculative Loads

5.9 Summary