Chapter 4 The Microarchitecture Level

4.1 An Example Microarchitecture

4.1.1 The Data Path

4.1.2 Microinstructions

4.1.3 Microinstruction Control: The Mic-1

4.2 An Example ISA: IJVM

4.2.1 Stacks

4.2.2 The IJVM Memory Model

4.2.3 The IJVM Instruction Set

4.2.4 Compiling Java to IJVM

4.3 An Example Implementation

4.3.1 Microinstructions and Notation

4.3.2 Implementation of IJVM Using the Mic-1

4.4 Design of the Microarchitecture Level

4.4.1 Speed versus Cost

4.4.2 Reducing the Execution Path Length

4.4.3 A Design with Prefetching: The Mic-2

4.4.4 A Pipelined Designed: The Mic-3

4.4.5 A Seven-Stage Pipeline: The Mic-4

4.5 Improving Performance

4.5.1 Cache Memory

4.5.2 Branch Prediction

4.5.3 Out-of-Order Execution and Register Renaming

4.5.4 Speculative Execution

4.6 Examples of the Microarchitecture Level

4.6.1 The Microarchitecture of the Pentium 4 CPU

4.6.2 The Microarchitecture of the UltraSPARC-III CU CPU

4.6.3 The Microarchitecture of the 8051 CPU

4.7 Comparison of the Pentium, UltraSPARC and 8051

4.8 Summary